In static random access memories (SRAMs) there has been recognized a problem of losing data in the case of a read following a write. This was addressed, for example, in U.S. Pat. No. 4,110,840, Abe et al, in which it was recognized that during a write the bit line pairs and the data lines reach or nearly reach the power supply voltages and that a read of a cell different than the one written could result in the loss of data in the cell being read. This is because of the capacitance of the bit lines. If a bit line pair is polarized to one logic state during the write cycle and the cell to be read is in another logic state, the capacitance of the bit lines can make it too difficult for the selected cell to reverse the polarity of the bit line pair to which it is connected with the result that the bit line pair reverses the contents of the cell instead of the cell reversing the polarity of the bit line pair.
The problem is not as severe for consecutive reads because a cell which is selected to be read does not polarize the bit line pair to which it is connected to the same extent as does the write circuitry during a write. Consequently, a cell which must be read after the bit lines have been separated by a memory cell does not face as difficult a task as does a cell which is read after a write.
SRAMs which utilize address transition techniques have developed another way of handling this problem. The read following write problem is only relevant if there is a change in memory location. With address transition techniques, the bit lines and data lines are equalized in response to at least any new word line being selected. Address transition detection circuitry provides a pulse in response to a least any row address change. This pulse is used to perform the desired equalization. The equalization must occur before the newly selected word line is enabled. Typically, it is necessary to add delay in the row decoding scheme to ensure that the new word line is not enabled until the equalization is complete. One way to reduce the amount of added delay in the row decoding scheme is to increase the speed of the address buffers. Increasing speed, however, has the undesirable effect of increasing power consumption. To be effective in this regard, each address buffer must be so increased in power consumption. The number of address buffers which are needed is related to the number of address locations. In an 8Kx8 SRAM for example there are 8192 addressable locations requiring 13 address buffers. To increase the speed of the address buffers then requires the increase in power consumption for all of them.